Consider the comparator circuit described in question A.2, but now for 8-bit binary numbers $x$ and $y$ that have been stored in 8-bit shift registers and are read serially, one bit per clock cycle, MSB first. Therefore, you may consider that the input to the sequential machine are two bit streams, $x_{i}$ and $y_{i}$ , MSB first. The output $z=(z_{1},z_{2},z_{3})$ of the comparator should be $z=(0,0,0)$ while the comparison is ongoing. Once the comparison end, the output should have the following values for at least one clock pulse: $z=(0,0,1)$ if $x<y$ , $z=(1,0,0)$ if $x>y$ , and $z=(0,1,0)$ if $x=y$ .

This circuit can be implemented by combining the following elements:

a 1-bit comparator with two bits $A$ and $B$ as inputs and the same 3-bit output $w$ as described in question A.2: given two input bits $A$ and $B$ , the output is $w=(0,0,1)$ if $A<B$ , $w=(1,0,0)$ if $A>B$ , and $w=(0,1,0)$ if $A=B$ ;
a 3-bit counter (also known as MOD-8 counter), which outputs a 3-bit binary number $c=(c_{2}$ , $c_{1}$ , $c_{0})$ with the count value from 0 to 7, which is incremented by 1 per clock cycle.
at most two D flip-flops;
a few combinatorial circuits to obtain the new states and the output from the input signals and the previous elements.

Design a sequential machine (Moore or Mealy type) that implements the 8-bit comparator circuit, with the appropriate motivation for your design by means of a state diagram, and explain its operation. Draw the resulting connections between all the elements, including the Boolean functions that give the new states and the output.

Note: the Boolean functions do not need to be in minimal SP-form.